Who Should Attend?
- Engineers needing to develop skills in the practical use of VHDL.
- Engineers with some practical VHDL expertise needing to acquire a more in-depth appreciation of the concepts involved.
- Analogue engineers needing an overview of modern VHDL techniques to enhance their analogue design skills.
Delegates should have a good overview of digital design techniques and have a good working knowledge of digital hardware design. No previous knowledge of VHDL or a software language is required.
Course Format
Part A (1.5days):
Covers VHDL basics, and is a web-based distance learning self-paced tutorial video with practical exercises.
Part B (3 days):
Covers development of a hardware image processing system, and is taught in a workshop training style (40% is presentation and the remaining 60% is practical hands-on).
Course Content
Part A consists of 4 Modules and covers the following:
- Capturing VHDL models of numerous, increasingly-complex digital components using modular and structured practical exercises and directly-related presentation material.
- Capturing powerful text-driven VHDL testbenches for behavioural simulation of VHDL models.
- Synthesis of all VHDL model examples to target technology, including hardware implementation and test.
- Reinforcing digital hardware design concepts and hardware implementation skills through:
- Use of a structured design, documentation and test methodology throughout;
- Analysis of synthesised schematic netlists created for all synthesised models;
- Feedback and discussion.
- Use of script-based automation and file-driven VHDL testbenching, from early stage, to improve productivity.
- Use of Modelsim simulator design debug features for detecting design bugs.
- Project files and VHDL template files provided: a streamlined, common design format, for high productivity.
Click here for full course content for each Module.
Part B consists of 40% presentations and 60% practical hands-on development of a hardware image processing system.
Presentations:
- Brief Recap of Part 1 Course Material;
- VHDL: debugging with Modelsim;
- VHDL for Finite State Machine description;
- Signals vs. Variables;
- VHDL Signal Resolution;
- VHDL types and type conversion;
- VHDL for tri-State control;
- Generics;
- Generate;
- Configurations;
Practical: Image Processing System
- Medium-complexity hardware image processing system.[specification]
- VHDL capture, testbench, simulation, synthesis, FPGA implementation and hardware test
- Structured design documentation, implementation and test strategy used throughout
Major Elements & Tasks:
| Module: |
Description: |
Activity (see glossary below): |
| displayCtrlr |
Multiplexed 7-segment display and LED controller |
C, S, I |
| CSRBlk |
Control and status register block |
C, S, I |
| IOCtrlr |
Serial (UART) interface and I/O controller » Parses host GUI commands and data |
C, FSM, S, I |
| datCtrlr |
Datapath (8-bit UART ⇒ 32-bit SRAM data bundle and vice-versa) |
C, S, I |
| memCtrlr |
SRAM datapath select and SRAM controller FSM |
C, FSM, S, BFM |
| dspBlk |
Image pixel subtractor (delta-frame generation) |
C, FSM, S |
| appliedVHDL |
Complete applied system integration |
C, S, I |
Glossary
| FSM |
Finite State Machine |
| C |
VHDL Capture |
| S |
Simulation |
| I |
Implementation |
| BFM |
VHDL Bus Functional Model |
Participants' Comments
"Excellent delivery."
"Good mix of lecture/lab."
"Extreme depth & breadth of knowledge."
"Enabled quick & relevant response to queries during lab work."
"Working through a 'real world' complex design was valuable."
"Initially, I thought the lab would be too difficult - this was not the case. "
"Project excellent - a very effective learning tool."
"Clear, helpful, interactive."
86% satisfaction rating - based on an average response over a series of nine categories
This course can be run in-house or as an open public course. If you would be interested in arranging an in-house VHDL course for your company, please contact the ITS-Ireland office.
For further information on this course see here.
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