Course Instructor:  Harry Veendrick

Who Should Attend?

The course is intended to be a complete and comprehensive tutorial on state-of-the-art CMOS ICs for engineers working in the various disciplines of the semiconductor research and industry communities: design, modelling, technology development, CAD development, test development, product engineering, failure analysis, reliability engineering and packaging, etc.

Course Aims

This course has been designed to:

• Provide a fully updated overview of the basics, physics, fabrication, design and applications of CMOS ICs into the nanometer range, including low-power/low-leakage, robust IC-design (reliability variability and signal integrity and EMC).
• Discuss technology/design scaling bottlenecks to 32nm CMOS and beyond.
• Bridge the gap between the design, test and technology communities.

Course Format

The course consists of four two-hour lectures each day over a five-day period. It includes exercises during the day and the evening and a final examination to be carried out at home and returned for assessment during the two weeks after the end of the course. If a sufficiently high standard is obtained, participants will receive an official certificate. The course text is Harry Veendrick's book 'Nanometer CMOS ICs - from Basics to ASICs' and each delegate will receive a free copy on the first day.

Course Content

The course is a bottom-up, hierarchical approach to the subject of basic circuit and systems design using standard CMOS technologies. Simple modelling techniques are used to gain understanding and intuition into the function of circuits. Computer simulation is used to predict circuit performance. Techniques suitable to enhanced performance using integrated circuit technology are used. In addition, the implications of IC fabrication are used whenever possible to associate the electrical performance with the physical attributes of the circuit.

Basic Principles:

• MOS physics
• Characteristics
• Equations
• Capacitances

Geometry Effects:

• Temperature behaviour
• Short- and narrow-channel effects
• Mobility reduction
• BiCMOS technology
• Subthreshold behaviour and leakage current mechanisms

CMOS Technology:

• Extensive lithography overview
• Basic CMOS processing steps
• Process flow
• From a basic nMOS process to a 45 nm CMOS process
• Future processes, SOI, finfet

CMOS Design:

• Extensive discussion on electrical, logic and layout design, with 50nm CMOS design rules and process cross sections.

CMOS Memories:

• Memory architectures, SRAM, DRAM, ROM, PROM, E(E)PROM, NAND- and NOR-flash memories, stand-alone and embedded memories.

VLSI and ASICs:

• Design flow, hierarchy levels
• IP cores, re-use, ASICs
• ASIC design styles: standard cell, gate array (sea-of-gates) designs, PLDs, (re)configurable logic, embedded FPGAs, etc.

Low-power:

• Battery overview
• Extensive discussion and complete overview of existing technology and design options for low power and low leakage.

Robustness of ICs:

• Extensive discussion regarding reliability and signal integrity issues: latch-up, punch-through, ESD protection circuits, hot-carrier degradation.
• Electromigration, NBTI, wire self-heating, clocking, timing, signal integrity, supply and substrate noise, power integrity, decoupling,cross-talk, noise margins, EMC, soft-errors and variability, etc.

Testing, Debugging, Failure Analysis and Yield, Packaging:

• Complete overview of testing, shmoo-plots, design for debug, basics of yield and simple model, packaging characteristics and trends, diagnosis techniques, state-of-the-art failure analysis techniques. Repair, focussed ion beam, etc.

Scaling Trends and Roadblocks:

• Costs and roadblocks for 65 nm technologies and beyond, speed and power trends, design, masks and processing costs, roadblocks and solutions, end of Moore's Law!

For information on the course tutor for this course see here.