Course Instructor:  Harry Veendrick

Who Should Attend?

This course is meant as a comprehensive tutorial on selected subjects of state-of-the-art CMOS ICs for engineers working in electronic product development and engineering and those who have to write and read product specifications, test samples, discuss technical details with suppliers and customers, etc. It will be of benefit to others who need a thorough understanding of ASIC development.

Course Aims

This course has been designed to:

• Provide a fully updated overview of the basics, physics, fabrication, design and applications of CMOS ICs into the nanometer range, including low-power/low-leakage, robust IC-design (reliability variability and signal integrity and EMC).
• Discuss technology/design scaling bottlenecks to 32nm CMOS and beyond.
• Aims to bridge the gap between the design, test and technology communities.

Course Format

The course consists of four two-hour lectures each day over a three-day period. It includes exercises during the day and the evening and a final examination to be carried out at home and returned for assessment during the two weeks after the end of the course. If a sufficiently high standard is obtained, participants will receive an official certificate. The course text is Harry Veendrick's book 'Nanometer CMOS ICs - from Basics to ASICs' and each delegate will receive a free copy on the first day.

Course Content

The course is a bottom-up, hierarchical approach to the subject of basic circuit and systems design using standard CMOS technologies. Simple modelling techniques are used to gain understanding and intuition into the function of circuits. Computer simulation is used to predict circuit performance. Techniques suitable to enhanced performance using integrated circuit technology are used. In addition, the implications of IC fabrication are used whenever possible to associate the electrical performance with the physical attributes of the circuit

Basic Principles:

• MOS physics
• Characteristics
• Equations
• Capacitances (short summary)

Geometry Effects:

• Temperature behaviour
• Transistor scaling aspects
• Subthreshold behaviour and leakage current mechanisms

CMOS Technology:

• lithography - basics and limitations
• Basic CMOS processing steps
• From a basic nMOS process to a 45 nm CMOS process

CMOS Design:

• Short summary of the basic principles of electrical and logic design (no layout design).

CMOS Memories:

• Memory architectures, SRAM, DRAM, ROM, PROM, E(E)PROM, NAND- and NOR-flash memories, stand-alone and embedded memories.

VLSI and ASICs:

• Short summary of design flow
• Hierarchy levels
• IP cores and re-use

Low-power:

• Battery overview
• Flavour of existing technology
• Design options for low power and low leakage

Robustness of ICs:

• Reliability Issues
• Latch-up, punch-through, ESD protection circuits
• Hot-carrier degradation
• Electromigration
• NBTI
• Quick summary of supply and substrate noise, power integrity, decoupling, cross-talk, noise margins, EMC, soft-errors and variability, etc.

Testing, Debugging, Failure Analysis and Yield, Packaging:

• Basics of testing
• Yield and packaging - characteristics and trends
• Flavour of diagnosis and state-of-the-art failure analysis techniques ...

Scaling Trends and Roadblocks:

• Costs and roadblocks for 65 nm technologies and beyond
• Speed and power trends
• Design, masks and processing costs
• Roadblocks and solutions
• End of Moore's Law!

For information on the course tutor for this course see here.